Ramp voltage generator and image sensing device including the same

ABSTRACT

A ramp voltage generator includes a first ramp voltage generation block suitable for generating a first ramp voltage with a first slope in response to a bias signal and a first ramp control signal, and a second ramp voltage generation block suitable for generating a second ramp voltage with a second slope corresponding to the first slope in response to the bias signal, a second ramp control signal, and a slope correction signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2015-0025611, filed on Feb. 24, 2015, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a semiconductordesign technology and, more particularly, to a ramp voltage generatorand an image sensing device including the same.

2. Description of the Related Art

Image sensing devices capture images using photosensitive properties ofsemiconductors. Image sensing devices are often classified intocharge-coupled device (CCD) image sensors and complementary metal-oxidesemiconductor (CMOS) image sensors. CMOS image sensors allow for bothanalog and digital control circuits to be directly realized on a singleintegrated circuit (IC), making CMOS image sensors the most widely usedtype of image sensor.

Electronic devices such mobile phones may be fabricated with built-inimage sensing devices. The image sensing devices need to perform highspeed operations to improve overall performance of the mobile apparatus.This has resulted in many specialized technologies being developed forimage sensing devices. Particularly, technologies for reducinganalog-to-digital converter (hereinafter, referred to as “ADC”) readouttimes of image sensing devices are being proposed.

For example, a 2-step ADC developed from a single-slope ADC has beenproposed. The single-slope ADC requires a clock with a cycle of“2¹⁰=1024” in order to output a digital signal of 10 bits, but the2-step ADC requires a clock with a cycle of “2³+2⁷=136” by outputting 3bits of the digital signal using a coarse clock and outputting the other7 bits of the digital signal using a fine clock. Ideally, the readouttime can be reduced by a ratio of “136/1024”. Since the coarse clock hasa frequency lower than that of the fine clock in order to ensure thesettling time of the coarse clock, the readout time is longer than theideal readout time. However, the readout time of the 2-step ADC may beeffectively reduced compared with the readout time of the single-slopeADC. In addition, since the 2-step ADC may be realized in a small area,it has been favored as a technology that can be applied to image sensingdevices with a high number of pixels that operate at high speed.

The 2-step ADC uses a coarse ramp voltage corresponding to the coarseclock and a fine ramp voltage corresponding to the fine clock. Forexample, the 2-step ADC outputs a digital signal of 3 bits correspondingto a voltage level of a pixel signal, which is an analog signal, basedon the coarse ramp voltage having a predetermined slope, and thenoutputs a digital signal of 7 bits corresponding to the voltage level ofthe pixel signal based on the fine ramp voltage having the predeterminedslope. Typically, an image sensing device includes a ramp voltagegenerator for generating the coarse ramp voltage and the fine rampvoltage.

FIG. 1 illustrates an Internal configuration diagram of a ramp voltagegenerator.

Referring to FIG. 1, the ramp voltage generator includes a sourcecurrent generation unit 11, a coarse ramp voltage generation unit 13,and a fine ramp voltage generation unit 15.

The source current generation unit 11 generates a first source currentI1 in response to a first bias signal VNB, and generates a second biassignal VPB corresponding to the first source current I1.

For example, the source current generation unit 11 includes a firstsinking section N1 and a first sourcing section P0. The first sinkingsection N1 is coupled between an output terminal of the second biassignal VPB and a ground voltage terminal VSS, and makes the first sourcecurrent I1 sink to the ground voltage terminal VSS in response to thefirst bias signal VNB. For example, the first sinking section N1includes a NMOS transistor having a gate coupled to an input terminal ofthe first bias signal VNB, and a drain and a source coupled between theoutput terminal of the second bias signal VPB and the ground voltageterminal VSS. The first sourcing section P0 is coupled between a powersupply voltage terminal VDD and the output terminal of the second biassignal VPB, and makes the source current I1 sourced from the powersupply voltage terminal VDD in response to the second bias signal VPB.For example, the first sourcing section P0 Includes a PMOS transistorhaving a gate and a drain coupled to the output terminal of the secondbias signal VPB, and a source coupled to the power supply voltageterminal VDD.

The coarse ramp voltage generation unit 13 generates a first mirrorcurrent I2 varied by a coarse unit (for example, corresponding to 128least significant bits (LSB)) in response to the second bias signal VPBand first to X^(th) coarse ramp control signals CR_CTRL<1:X>, andgenerates a coarse ramp voltage VCR based on the first mirror currentI2.

For example, the coarse ramp voltage generation unit 13 includes a firstmirroring section P1 to PX, a first switching section SW1 to SWX, and afirst resistor section R_CR. The first mirroring section P1 to PX iscoupled between the power supply voltage terminal VDD and first toX^(th) mirroring nodes MN1 to MNX, and resources the first mirrorcurrent I2 in response to the second bias signal VPB. For example, thefirst mirroring section P1 to PX includes first to X^(th) PMOStransistors respectively having gates coupled to an input terminal ofthe second bias signal VPB and sources and drains coupled between thepower supply voltage terminal VDD and the first to X^(th) mirroringnodes MN1 to MNX. The first switching section SW1 to SWX is coupledbetween the first to X^(th) mirroring nodes MN1 to MNX and an outputterminal of the coarse ramp voltage VCR, and generates the first mirrorcurrent I2 decreased by the coarse unit during a coarse conversionperiod in response to the first to X^(th) coarse ramp control signalsCR_CTRL<1:X>. For example, the first switching section SW1 to SWXincludes first to X^(th) switching elements which are sequentially openduring the coarse conversion period in response to the first to X^(th)coarse ramp control signals CR_CTRL<1:X>. The first resistor sectionR_CR may be coupled between the output terminal of the coarse rampvoltage VCR and the ground voltage terminal VSS. For example, the firstresistor section R_CR includes a resistance element.

The fine ramp voltage generation unit 15 generates a second mirrorcurrent I3 varied by a fine unit (for example, corresponding to 1 LSB)in response to the second bias signal VPB and first to Z^(th) fine rampcontrol signals FR_CTRL<1:Z>, and generates a fine ramp voltage VFRbased on the second mirror current I3.

For example, the fine ramp voltage generation unit 15 includes a secondmirroring section PX+1 to PX+Z, a second switching section SWX+1 toSWX+Z, and a second resistor section R_FR. The second mirroring sectionPX+1 to PX+Z is coupled between the power supply voltage terminal VDDand (X+1)^(th) to (X+Z)^(th) mirroring nodes MNX+1 to MNX+Z, andresources the second mirror current I3 in response to the second biassignal VPB. For example, the second mirroring section PX+1 to PX+Zincludes (X+1)^(th) to (X+Z)^(th) PMOS transistors respectively havinggates coupled to the input terminal of the second bias signal VPB andsources and drains coupled between the power supply voltage terminal VDDand the (X+1)^(th) to (X+Z)^(th) mirroring nodes MNX+1 to MNX+Z. Thesecond switching section SWX+1 to SWX+Z is coupled between the(X+1)^(th) to (X+Z)^(th) mirroring nodes MNX+1 to MNX+Z and an outputterminal of the fine ramp voltage VFR, and generates the second mirrorcurrent I3 increased by the fine unit during a fine conversion period inresponse to the first to Z^(th) fine ramp control signals FR_CTRL<1:Z>.For example, the second switching section SWX+1 to SWX+Z includes(X+1)^(th) to (X+Z)^(th) switching elements which are sequentiallyclosed during fine conversion period in response to the first to Z^(th)fine ramp control signals FR_CTRL<1:Z>. The second resistor section R_FRmay be coupled between the output terminal of the fine ramp voltage VFRand the ground voltage terminal VSS. For example, the second resistorsection R_FR includes a resistance element.

An image sensing device configured as above may have a mismatch betweenthe coarse ramp voltage generation unit 13 and the fine ramp voltagegeneration unit 15. For example, a process mismatch occurs between thefirst to X^(th) PMOS transistors included in the first mirroringsections P1 to PX and the (X+1)^(th) to (X+Z)^(th) PMOS transistorsincluded in the second mirroring sections PX+1 to PX+Z, or a processmismatch occurs between a load resistor of the coarse ramp voltagegeneration unit 13 and a load resistor of the fine ramp voltagegeneration unit 15.

For this reason, when a mismatch occurs between the coarse ramp voltagegeneration unit 13 and the fine ramp voltage generation unit 15, amismatch also occurs between the coarse ramp voltage VCR and the fineramp voltage VFR. In this case, a circuit using the coarse ramp voltageVCR and the fine ramp voltage VFR, for example, the 2-step ADC outputs adigital signal corresponding to a missing code. Graphs (A) and (B) ofFIG. 2 illustrate the relation between the range of an analog signal(that is, ADC range) and a corresponding digital signal (i.e., countcode) to which the 2-step ADC may convert the analog signal. Forexample, when the slope of the fine ramp voltage VFR is lower than thatof the coarse ramp voltage VCR, a linearity error may occur asillustrated in graph (A) of FIG. 2. When the slope of the fine rampvoltage VFR is higher than that of the coarse ramp voltage VCR, alinearity error may occur as illustrated in graph (B) of FIG. 2.

Therefore, when the aforementioned linearity error occurs, the 2-stepADC outputs a digital signal corresponding to a missing code inconverting an analog signal.

SUMMARY

Various embodiments are directed to a ramp voltage generator capable ofcorrecting a mismatch between a coarse ramp voltage and a fine rampvoltage and an image sensing device including the same.

In an embodiment, a ramp voltage generator may include a first rampvoltage generation block suitable for generating a first ramp voltagewith a first slope in response to a bias signal and a first ramp controlsignal, and a second ramp voltage generation block suitable forgenerating a second ramp voltage with a second slope corresponding tothe first slope in response to the bias signal, a second ramp controlsignal, and a slope correction signal.

The second slope may be substantially equal to the first slope.

The ramp voltage generator may further include a correction blocksuitable for storing the slope correction signal.

The first ramp control signal may be generated based on a first clock,and the second ramp control signal may be generated based on a secondclock with a frequency higher than the frequency of the first clock.

In an embodiment, a ramp voltage generator may include a first sourcecurrent generation unit suitable for generating a first source currentin response to a first bias signal, and generating a second bias signalcorresponding to the first source current, a first ramp voltagegeneration unit suitable for generating a first mirror current varied bya coarse unit in response to the second bias signal and a coarse rampcontrol signal, and generating a coarse ramp voltage having a firstslope based on the first mirror current, a second source currentgeneration unit suitable for generating a second source currentcorrected based on the first slope in response to the first bias signaland a slope correction signal, and generating a third bias signalcorresponding to the second source current, and a second ramp voltagegeneration unit suitable for generating a second mirror current variedby a fine unit in response to the third bias signal and a fine rampcontrol signal, and generating a fine ramp voltage having the firstslope based on the second mirror current.

The second source current generation unit may include a second sinkingsection coupled between an output terminal of the third bias signal anda ground voltage terminal, wherein the second source current sinks tothe ground voltage terminal in response to the first bias signal, aplurality of second sourcing sections coupled between a power supplyvoltage terminal and a plurality of second sourcing nodes, respectively,wherein the second source current is sourced from the power supplyvoltage terminal in response to the third bias signal, and a pluralityof second switching sections coupled between the plurality of secondsourcing nodes, respectively, and the output terminal of the third biassignal, and suitable for being selectively switched in response to theslope correction signal.

The second ramp voltage generation unit may include a second mirroringsection coupled between a power supply voltage terminal and a pluralityof second mirroring nodes, wherein the second source current is sourcedfrom the power supply voltage terminal in response to the third biassignal; a third switching section coupled between the plurality ofsecond mirroring nodes and an output terminal of the fine ramp voltage,and suitable for being sequentially switched in response to the fineramp control signal, and a second resistor section coupled between theoutput terminal of the fine ramp voltage and a ground voltage terminal.

The ramp voltage generator may further include a storage unit suitablefor storing the slope correction signal.

The first source current generation unit may include a first sinkingsection coupled between an output terminal of the second bias signal anda ground voltage terminal, wherein the first source current sinks to theground voltage terminal in response to the first bias signal, and afirst sourcing section coupled between a power supply voltage terminaland the output terminal of the second bias signal, wherein the firstsource current is sourced from the power supply voltage terminal inresponse to the second bias signal.

The first ramp voltage generation unit may include a first mirroringsection coupled between a power supply voltage terminal and a pluralityof first mirroring nodes, wherein the first source current is sourcedfrom the power supply voltage terminal in response to the second biassignal, a first switching section coupled between the plurality of firstmirroring nodes and an output terminal of the coarse ramp voltage, andsuitable for being sequentially switched in response to the coarse rampcontrol signal, and a first resistor section coupled between the outputterminal of the coarse ramp voltage and a ground voltage terminal.

The coarse ramp control signal may be generated based on a first clock,and the fine ramp control signal may be generated based on a secondclock with a frequency higher than the frequency of the first clock.

In an embodiment, an image sensing device may include a pixel arraysuitable for generating an image signal, an analog-to-digital convertersuitable for generating a digital signal corresponding to the imagesignal by using a coarse ramp voltage and a fine ramp voltage, and aramp voltage generator suitable for generating the coarse ramp voltagehaving a first slope and the fine ramp voltage having a second slopecorrected based on the first slope in response to a bias signal, acoarse ramp control signal, and a fine ramp control signal.

The second slope may be substantially equal to the first slope.

The ramp voltage generator may include a correction block suitable forstoring a slope correction signal, a first ramp voltage generation blocksuitable for generating the coarse ramp voltage in response to the biassignal and the coarse ramp control signal, and a second ramp voltagegeneration block suitable for generating the fine ramp voltage inresponse to the bias signal, the fine ramp control signal, and the slopecorrection signal.

The second ramp voltage generation block may include a second sourcecurrent generation unit suitable for generating a second source currentcorrected based on the first slope in response to a first bias signaland the slope correction signal, and generating a third bias signalcorresponding to the second source current, and a second ramp voltagegeneration unit suitable for generating a second mirror current variedby a fine unit in response to the third bias signal and the fine rampcontrol signal, and generating the fine ramp voltage based on the secondmirror current.

The second source current generation unit may include a second sinkingsection coupled between an output terminal of the third bias signal anda ground voltage terminal, wherein the second source current sinks tothe ground voltage terminal in response to the first bias signal, aplurality of second sourcing sections coupled between a power supplyvoltage terminal and a plurality of second sourcing nodes, respectively,wherein the second source current is sourced from the power supplyvoltage terminal in response to the third bias signal, and a pluralityof second switching sections coupled between the plurality of secondsourcing nodes, respectively, and the output terminal of the third biassignal, and suitable for being selectively switched in response to theslope correction signal.

The second ramp voltage generation unit may include a second mirroringsection coupled between a power supply voltage terminal and a pluralityof second mirroring nodes, wherein the second source current is sourcedfrom the power supply voltage terminal in response to the third biassignal, a third switching section coupled between the plurality ofsecond mirroring nodes and an output terminal of the fine ramp voltage,and suitable for being sequentially switched in response to the fineramp control signal, and a second resistor section coupled between theoutput terminal of the fine ramp voltage and a ground voltage terminal.

The first ramp voltage generation block may include a first sourcecurrent generation unit suitable for generating a first source currentin response to a first bias signal, and generating a second bias signalcorresponding to the first source current, and a first ramp voltagegeneration unit suitable for generating a first mirror current varied bya coarse unit in response to the second bias signal and the coarse rampcontrol signal, and generating the coarse ramp voltage based on thefirst mirror current.

The first source current generation unit may include a first sinkingsection coupled between an output terminal of the second bias signal anda ground voltage terminal, wherein the first source current sinks to theground voltage terminal in response to the first bias signal, and afirst sourcing section coupled between a power supply voltage terminaland the output terminal of the second bias signal, wherein the firstsource current is sourced from the power supply voltage terminal inresponse to the second bias signal.

The first ramp voltage generation unit may include a first mirroringsection coupled between a power supply voltage terminal and a pluralityof first mirroring nodes, wherein the first source current is sourcedfrom the power supply voltage terminal in response to the second biassignal, a first switching section coupled between the plurality of firstmirroring nodes and an output terminal of the coarse ramp voltage, andsuitable for being sequentially switched in response to the coarse rampcontrol signal, and a first resistor section coupled between the outputterminal of the coarse ramp voltage and a ground voltage terminal.

In accordance with the embodiment of the present invention, a mismatchbetween a coarse ramp voltage and a fine ramp voltage is corrected, sothat the linearity of the slope of the coarse ramp voltage and the fineramp voltage is improved.

Moreover, in accordance with an embodiment of the present invention, itis possible to generate a digital signal corresponding to a proper codein converting an analog signal to a digital signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an internal configuration diagram of a conventional rampvoltage generator.

FIG. 2 is a graph for explaining the operation of a ramp voltagegenerator illustrated in FIG. 1.

FIG. 3 is a block configuration diagram of an image sensing device inaccordance with an embodiment of the present invention.

FIG. 4 is a block configuration diagram of an analog-to-digitalconverter illustrated in FIG. 3.

FIG. 5 is a block configuration diagram of a ramp voltage generatorillustrated in FIG. 3.

FIG. 6 is an internal configuration diagram of a coarse ramp voltagegeneration block illustrated in FIG. 5.

FIG. 7 is an internal configuration diagram of a fine ramp voltagegeneration block illustrated in FIG. 5.

FIG. 8 is a timing diagram for explaining the operation of an imagesensing device illustrated in FIG. 3.

FIG. 9 is a graph for explaining the improvement of a ramp voltagegenerator illustrated in FIG. 5.

DETAILED DESCRIPTION

Various embodiments will be described below in more detail withreference to the accompanying drawings. The present invention may,however, be embodied in different forms and should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the present invention to those skilled inthe art. Throughout the disclosure, like reference numerals refer tolike parts throughout the various figures and embodiments of the presentinvention.

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as being“on” a second layer or “on” a substrate, it not only refers to where thefirst layer is formed directly on the second layer or the substrate butalso to where a third layer exists between the first layer and thesecond layer or the substrate.

Hereinafter, a ramp voltage generator and an image sensing deviceincluding the same in accordance with an embodiment of the presentInvention will be described in more detail.

FIG. 3 illustrates a block configuration diagram of an image sensingdevice in accordance with an embodiment of the present invention.

Referring to FIG. 3, an image sensing device 100 may include a pixelarray 110, an analog-to-digital converter (ADC) 120, and a ramp voltagegenerator 130.

The pixel array 110 may include N×M pixels (not illustrated) arranged ina row direction and a column direction (N and M being natural numbers).The pixel array 110 may sequentially output first to N^(th) pixelsignals VPX<1:N> in units of rows M times.

The analog-to-digital converter 120 may generate first to N^(th) digitalsignals DOUT<1:N> corresponding to the first to N^(th) pixel signalsVPX<1:N> by using a coarse ramp voltage VCR and a fine ramp voltage VFR.For example, the analog-to-digital converter 120 may include a 2-stepADC.

The ramp voltage generator 130 may generate the coarse ramp voltage VCRhaving a first slope and the fine ramp voltage VFR having a second slopecorrected based on the first slope in response to a first bias signalVNB, first to X^(th) coarse ramp control signals CR_CTRL<1:X>, and firstto Z^(th) fine ramp control signals FR_CTRL<1:Z>.

FIG. 4 illustrates a block configuration diagram of theanalog-to-digital converter 120 illustrated in FIG. 3.

Referring to FIG. 4, the analog-to-digital converter 120 may include acomparison block 121 and a counter block 123.

The comparison block 121 may include first to N^(th) comparison units(not illustrated) corresponding to the first to N^(th) pixel signalsVPX<1:N>. The first to N^(th) comparison units may respectively receivethe first to N^(th) pixel signals VPX<1:N>, and receive the coarse rampvoltage VCR and the fine ramp voltage VFR in common. The first to N^(th)comparison units may compare respective pixel signals with the coarseramp voltage VCR during a coarse conversion period, compare therespective pixel signals with the fine ramp voltage VFR during a fineconversion period, and generate first to N^(th) comparison resultsignals VOUT<1:N> based on comparison results during the coarse and fineconversion periods. For example, the first comparison unit may comparethe first pixel signal VPX<1> with the coarse ramp voltage VCR, and mayperform zero crossing for the first comparison result signal VOUT<1>when the first pixel signal VPX<1> is substantially equal to the coarseramp voltage VCR as a result of the comparison. Based on the comparisonresult of the first pixel signal VPX<1> and the coarse ramp voltage VCR,the first comparison unit may compare the first pixel signal VPX<1> withthe fine ramp voltage VFR, and may perform zero crossing for the firstcomparison result signal VOUT<1> again when the first pixel signalVPX<1> is substantially equal to the fine ramp voltage VFR as a resultof the comparison.

The counter block 123 may include first to N^(th) counting units (notillustrated) corresponding to the first to N^(th) comparison resultsignals VOUT<1:N>. The first to N^(th) counting units may count thefirst to N^(th) comparison result signals VOUT<1:N>, and generate thefirst to N^(th) digital signals DOUT<1:N> corresponding to the countingresult. For example, the first counting unit may count a coarse clock(not illustrated) for a period before the first comparison result signalVOUT<1> is subjected to first zero crossing during the coarse conversionperiod, count a fine clock (not illustrated) for a period before thefirst comparison result signal VOUT<1> is subjected to second zerocrossing during the fine conversion period, and generate the firstdigital signal DOUT<1> based on counting results.

FIG. 5 illustrates a block configuration diagram of the ramp voltagegenerator 130 illustrated in FIG. 3.

Referring to FIG. 5, the ramp voltage generator 130 may include a coarseramp voltage generation block 131, a fine ramp voltage generation block133, and a correction block 135.

The coarse ramp voltage generation block 131 may generate the coarseramp voltage VCR in response to the first bias signal VNB and the firstto X^(th) coarse ramp control signals CR_CTRL<1:X>. For example, thecoarse ramp voltage generation block 131 may generate the coarse rampvoltage VCR in response to the coarse clock during the coarse conversionperiod, where the voltage level of the coarse ramp voltage VCR drops by128 LSB.

The fine ramp voltage generation block 133 may generate the fine rampvoltage VFR in response to the first bias signal VNB, first to Z^(th)fine ramp control signals FR_CTRL<1:Z>, and first to Y^(th) slopecorrection signals SCAL<1:Y>. For example, the fine ramp voltagegeneration block 133 may generate the fine ramp voltage VFR in responseto the fine clock during the fine conversion period, where the voltagelevel of the fine ramp voltage VFR rises by 1 LSB.

The correction block 135 may store the first to Y^(th) slope correctionsignals SCAL<1:Y> previously set by a user. For example, the correctionblock 135 may include a register, a fuse circuit and the like.

FIG. 6 illustrates an internal configuration diagram of the coarse rampvoltage generation block 131 illustrated in FIG. 5.

Referring to FIG. 6, the coarse ramp voltage generation block 131 mayinclude a first source current generation unit 131_1 and a coarse rampvoltage generation unit 131_3.

The first source current generation unit 131_1 may generate a firstsource current I11 in response to the first bias signal VNB, andgenerate a second bias signal VPB_CR corresponding to the first sourcecurrent I11.

For example, the first source current generation unit 131_1 may includea first sinking section NCR1 and a first sourcing section PCR0. Thefirst sinking section NCR1 may be coupled between an output terminal ofthe second bias signal VPB_CR and a ground voltage terminal VSS, and maymake the first source current I11 sink to the ground voltage terminalVSS in response to the first bias signal VNB. For example, the firstsinking section NCR1 may include a NMOS transistor having a gate coupledto an input terminal of the first bias signal VNB and a drain and asource coupled between the output terminal of the second bias signalVPB_CR and the ground voltage terminal VSS. The first sourcing sectionPCR0 may be coupled between a power supply voltage terminal VDD and theoutput terminal of the second bias signal VPB_CR, and may make the firstsource current I11 sourced from the power supply voltage terminal VDD inresponse to the second bias signal VPB_CR. For example, the firstsourcing section PCR0 may include a PMOS transistor having a gate and adrain coupled to the output terminal of the second bias signal VPB_CRand a source coupled to the power supply voltage terminal VDD.

The coarse ramp voltage generation unit 131_3 may generate a firstmirror current I22 varied by a coarse unit (which may correspond to 128LSB) in response to the second bias signal VPB_CR and the first toX^(th) coarse ramp control signals CR_CTRL<1:X>, and generate the coarseramp voltage VCR based on the first mirror current I22.

For example, the coarse ramp voltage generation unit 131_3 may include afirst mirroring section PCR1 to PCRX, a first switching section SW21 toSW2X, and a first resistor section R_CR. The first mirroring sectionPCR1 to PCRX is coupled between the power supply voltage terminal VDDand first to X^(th) mirroring nodes CN1 to CNX, and resources the firstmirror current I22 in response to the second bias signal VPB_CR. Forexample, the first mirroring section PCR1 to PCRX includes first toX^(th) PMOS transistors respectively having gates coupled to an inputterminal of the second bias signal VPB_CR and sources and drains coupledbetween the power supply voltage terminal VDD and the first to X^(th)mirroring nodes CN1 to CNX. The first switching section SW21 to SW2X maybe coupled between the first to X^(th) mirroring nodes CN1 to CNX and anoutput terminal of the coarse ramp voltage VCR, and may generate thefirst mirror current I22 decreased by the coarse unit during the coarseconversion period in response to the first to X^(th) coarse ramp controlsignals CR_CTRL<1:X>. For example, the first switching section SW21 toSW2X may include first to X^(th) switching elements which sequentiallyopen during the coarse conversion period in response to the first toX^(th) coarse ramp control signals CR_CTRL<1:X>. The first resistorsection R_CR may be coupled between the output terminal of the coarseramp voltage VCR and the ground voltage terminal VSS. For example, thefirst resistor section R_CR may include a resistance element.

FIG. 7 illustrates an internal configuration diagram of the fine rampvoltage generation block 133 illustrated in FIG. 5.

Referring to FIG. 7, the fine ramp voltage generation block 133 mayinclude a second source current generation unit 133_1 and a fine rampvoltage generation unit 133_3.

The second source current generation unit 133_1 may generate a secondsource current I33 corrected based on the first slope in response to thefirst bias signal VNB and the first to Y^(th) slope correction signalsSCAL<1:Y>, and generate a third bias signal VPB_FR corresponding to thesecond source current I33.

For example, the second source current generation unit 133_1 may includea second sinking section NFR1, a second sourcing section PNR1 to PNRY,and a second switching section SW31 to SW3Y. The second sinking sectionNFR1 may be coupled between an output terminal of the third bias signalVPB_FR and the ground voltage terminal VSS, and may make the secondsource current I33 sink to the ground voltage terminal VSS in responseto the first bias signal VNB. For example, the second sinking sectionNFR1 may include a NMOS transistor having a gate coupled to the inputterminal of the first bias signal VNB and a drain and a source coupledbetween the output terminal of the third bias signal VPB_FR and theground voltage terminal VSS. The second sourcing section PNR1 to PNRYmay be coupled between the power supply voltage terminal VDD and firstto Y^(th) sourcing nodes CALN1 to CALNY, and may make the second sourcecurrent I33 sourced from the power supply voltage terminal VDD inresponse to the third bias signal VPB_FR. For example, the secondsourcing section PNR1 to PNRY may include first to Y^(th) PMOStransistors respectively having gates coupled to the output terminal ofthe third bias signal VPB_FR and sources and drains coupled between thepower supply voltage terminal VDD and the first to Y^(th) sourcing nodesCALN1 to CALNY. The second switching section SW31 to SW3Y may includefirst to Y^(th) switching elements coupled between the respective firstto Y^(th) sourcing nodes CALN1 to CALNY and the output terminal of thethird bias signal VPB_FR, and selectively switched in response to thefirst to Y^(th) slope correction signals SCAL<1:Y>.

The fine ramp voltage generation unit 133_3 may generate a second mirrorcurrent I44 varied by a fine unit (which may correspond to 1 LSB) inresponse to the third bias signal VPB_FR and the first to Z^(th) fineramp control signals FR_CTRL<1:Z>, and generate the fine ramp voltageVFR based on the second mirror current I44.

For example, the fine ramp voltage generation unit 133_3 may include asecond mirroring section PFR1 to PFRZ, a third switching section SW41 toSW4Z, and a second resistor section R_FR. The second mirroring sectionPFR1 to PFRZ may be coupled between the power supply voltage terminalVDD and first to Z^(th) mirroring nodes FN1 to FNZ, and may resource thesecond mirror current I44 in response to the third bias signal VPB_FR.For example, the second mirroring section PFR1 to PFRZ may include firstto Z^(th) PMOS transistors respectively having gates coupled to an inputterminal of the third bias signal VPB_FR and sources and drains coupledbetween the power supply voltage terminal VDD and the first to Z^(th)mirroring nodes FN1 to FNZ. The third switching section SW41 to SW4Z maybe coupled between the first to Z^(th) mirroring nodes FN1 to FNZ and anoutput terminal of the fine ramp voltage VFR, and may generate thesecond mirror current I44 increased by the fine unit during the fineconversion period in response to the first to Z^(th) fine ramp controlsignals FR_CTRL<1:Z>. For example, the third switching section SW41 toSW4Z may include first to Z^(th) switching elements which aresequentially closed during the fine conversion period in response to thefirst to Z^(th) fine ramp control signals FR_CTRL<1:Z>. The secondresistor section R_FR may be coupled between the output terminal of thefine ramp voltage VFR and the ground voltage terminal VSS. For example,the second resistor section R_FR may include a resistance element.

Hereinafter, the operation of the image sensing device 100 having theaforementioned configuration in accordance with the embodiment of thepresent invention will be described.

In the embodiment of the present invention, the general operation of theimage sensing device 100 for the first pixel signal VPX<1> will bedescribed with reference with FIG. 8 and FIG. 9.

FIG. 8 illustrates a timing diagram for explaining the operation of theimage sensing device 100 in accordance with the embodiment of thepresent invention, and FIG. 9 illustrates a graph for explaining how thelinearity of digital signals (for example, DOUT<1>) outputted from theanalog-to-digital converter 120 is improved as the slope of the fineramp voltage VFR is corrected.

The first to Y^(th) slope correction signals SCAL<1:Y> may be set inadvance in the correction block 135. For example, the slope of the fineramp voltage VFR may be measured through a test or a simulation, and thefirst to Y^(th) slope correction signals SCAL<1:Y> corresponding to themeasurement result may be set in advance in the correction block 135 bya user.

In such a state, referring to FIG. 8, the analog-to-digital converter120 may measure a voltage level of the first pixel signal VPX<1>outputted from the pixel array 110 based on the coarse ramp voltage VCRduring the coarse conversion period, and generate the first digitalsignal DOUT<1> corresponding to the measurement result. For example, thecomparison block 121 may compare the voltage level of the first pixelsignal VPX<1> with the coarse ramp voltage VCR with a voltage leveldropping by the coarse unit (for example, 128 LSB), and perform zerocrossing for the first comparison result signal VOUT<1> when the voltagelevel of the coarse ramp voltage VCR is lower than the voltage level ofthe first pixel signal VPX<1> as a result of the comparison.Furthermore, the counter block 123 may count a coarse clock (notillustrated) for a period before the first comparison result signalVOUT<1> is subjected to zero crossing during the coarse conversionperiod, and generate a count code of 3 bits corresponding to thecounting result as the first digital signal DOUT<1>.

Subsequently, the analog-to-digital converter 120 may measure thevoltage level of the first pixel signal VPX<1> based on the fine rampvoltage VFR during the fine conversion period, and generate the firstdigital signal DOUT<1> corresponding to the measurement result. Forexample, the comparison block 121 may compare the voltage level of thefirst pixel signal VPX<1> with the fine ramp voltage VFR with a voltagelevel rising by the fine unit (for example, 1 LSB), and perform zerocrossing for the first comparison result signal VOUT<1> when the voltagelevel of the fine ramp voltage VFR is higher than the voltage level ofthe first pixel signal VPX<1> as a result of the comparison. Thecomparison block 121 may store the level VS of the coarse ramp voltageVCR when it is lower than the voltage level of the first pixel signalVPX<1> in the coarse conversion period, and compare the fine rampvoltage VFR rising by the fine unit from the level VS with the voltagelevel of the first pixel signal VPX<1>. Furthermore, the counter block123 may count a fine clock (not illustrated) for a period before thefirst comparison result signal VOUT<1> is subjected to zero crossingduring the fine conversion period, and generate a count code of 7 bitscorresponding to the counting result as the first digital signalDOUT<1>.

The ramp voltage generator 130 may generate the coarse ramp voltage VCRwith a voltage level dropping by the coarse unit in response to thefirst to X^(th) coarse ramp control signals CR_CTRL<1:X> during thecoarse conversion period, and generate the fine ramp voltage VFR with avoltage level rising by the fine unit in response to the first to Z^(th)fine ramp control signals FR_CTRL<1:Z> during the fine conversionperiod. Particularly, the ramp voltage generator 130 may generate thefine ramp voltage VFR with a corrected slop in response to the first toY^(th) slope correction signals SCAL<1:Y> to correspond to the slope ofthe coarse ramp voltage VCR, during the fine conversion period. Theoperation of the ramp voltage generator 130 will be described in moredetail below.

The coarse ramp voltage generation block 131 may generate the coarseramp voltage VCR with a voltage level dropping by the coarse unit inresponse to the first bias signal VNB and the first to X^(th) coarseramp control signals CR_CTRL<1:X> during the coarse conversion period.

For example, the first sinking section NCR1 may make the first sourcecurrent I11 sink to the ground voltage terminal VSS in response to thefirst bias signal VNB, and the first sourcing section PCR0 may make thefirst source current I11 sourced from the power supply voltage terminalVDD in response to the second bias signal VPB_CR. The first mirroringsection PCR1 to PCRX may make the first mirror current I22 sourced fromthe power supply voltage terminal VDD in response to the second biassignal VPB_CR, and the first to X^(th) switching elements included inthe first switching section SW21 to SW2X may sequentially open duringthe coarse conversion period in response to the first to X^(th) coarseramp control signals CR_CTRL<1:X>, and may generate the first mirrorcurrent I22 sequentially decreased by the coarse unit. The coarse rampvoltage VCR with a voltage level dropping by the coarse unit incorrespondence to the first mirror current I22 may then be generated.

Next, the fine ramp voltage generation block 133 may generate the fineramp voltage VFR with a voltage level rising by the fine unit inresponse to the first bias signal VNB, the first to Z^(th) fine rampcontrol signals FR_CTRL<1:Z>, and the first to Y^(th) slope correctionsignals SCAL<1:Y> during the fine conversion period.

For example, the second sinking section NFR1 may sink the second sourcecurrent I33 to the ground voltage terminal VSS in response to the firstbias signal VNB, and the second sourcing section PNR1 to PNRY maygenerate the second source current I33 sourced from the power supplyvoltage VDD in response to the third bias signal VPB_FR. The first toY^(th) switching elements included in the second switching section SW31to SW3Y may then be selectively opened or closed in response to thepreset first to Y^(th) slope correction signals SCAL<1:Y>, and maycorrect the voltage level of the third bias signal VPB_FR. Asillustrated in a graph (A) of FIG. 9, when the slope of the fine rampvoltage VFR is higher than the slope of the coarse ramp voltage VCR, thenumber of switching elements closed among the first to Y^(th) switchingelements is increased, so that the voltage level of the third biassignal VPB_FR may be corrected to be increased. Thus, a unit currentamount (corresponding to an amount of current flowing through each thefirst to Z^(th) mirroring nodes FN1 to FNZ) of the second mirror currentI44 is reduced, so that the slope of the fine ramp voltage VFR may becorrected to be low. However, as illustrated in a graph (B) of FIG. 9,when the slope of the fine ramp voltage VFR is lower than the slope ofthe coarse ramp voltage VCR, the number of switching elements open amongthe first to Y^(th) switching elements is increased, so that the voltagelevel of the third bias signal VPB_FR may be corrected to be dropped.Thus, the unit current amount of the second mirror current I44 isincreased, so that the slope of the fine ramp voltage VFR may becorrected to be high.

The second mirroring section PFR1 to PFRZ may cake the second mirrorcurrent I44 sourced from the power supply voltage terminal VDD inresponse to the third bias signal VPB_FR, and the first to Z^(th)switching elements included in the third switching section SW41 to SW4Zmay be sequentially closed during the fine conversion period in responseto the first to Z^(th) fine ramp control signals FR_CTRL<1:Z>, and maygenerate the second mirror current I44 sequentially increased by thefine unit. At this time, the fine ramp voltage VFR with a voltage levelrising by the fine unit in correspondence to the second mirror currentI44 may be generated.

In accordance with the embodiment of the present invention as describedabove, the voltage level of the third bias signal VPB_FR required forgenerating the fine ramp voltage VFR is adjusted and thus the slope ofthe fine ramp voltage VFR and the slope of the coarse ramp voltage VCRare identical so that it is possible to correct a mismatch between thecoarse ramp voltage VCR and the fine ramp voltage VFR.

Although various embodiments have been described for illustrativepurposes, it will be apparent to those skilled in the art that variouschanges and modifications may be made without departing from the spiritand scope of the invention as defined in the following claims.

For example, in the embodiments of the present invention, the fine rampvoltage is corrected; however, the present invention is not limitedthereto, and the coarse ramp voltage may be corrected.

Furthermore, in the embodiments of the present invention, the secondsourcing section is controlled to correct the slope of the fine rampvoltage; however, the present invention is not limited thereto, and thesecond sinking section may be controlled to correct the slope of thefine ramp voltage.

Furthermore, in the embodiments of the present invention, an imagesensing device has been described as an example; however, the presentinvention is not limited thereto, and the present invention can beapplied to all devices and circuits using a coarse ramp voltage and afine ramp voltage.

What is claimed is:
 1. A ramp voltage generator comprising: a first rampvoltage generation block suitable for generating a first ramp voltagewith a first slope in response to a bias signal and a first ramp controlsignal; and a second ramp voltage generation block suitable forgenerating a second ramp voltage with a second slope corresponding tothe first slope in response to the bias signal, a second ramp controlsignal, and a slope correction signal.
 2. The ramp voltage generator ofclaim 1, wherein the second slope is substantially equal to the firstslope.
 3. The ramp voltage generator of claim 1, further comprising: acorrection block suitable for storing the slope correction signal. 4.The ramp voltage generator of claim 1, wherein the first ramp controlsignal is generated based on a first clock, and the second ramp controlsignal is generated based on a second clock that has a higher frequencythan that of the first clock.
 5. A ramp voltage generator comprising: afirst source current generation unit suitable for generating a firstsource current in response to a first bias signal, and generating asecond bias signal corresponding to the first source current; a firstramp voltage generation unit suitable for generating a first mirrorcurrent that is varied by a coarse unit in response to the second biassignal and a coarse ramp control signal, and generating a coarse rampvoltage having a first slope based on the first mirror current; a secondsource current generation unit suitable for generating a second sourcecurrent that is corrected based on the first slope in response to thefirst bias signal and a slope correction signal, and generating a thirdbias signal corresponding to the second source current; and a secondramp voltage generation unit suitable for generating a second mirrorcurrent that is varied by a fine unit in response to the third biassignal and a fine ramp control signal, and generating a fine rampvoltage having the first slope based on the second mirror current. 6.The ramp voltage generator of claim 5, wherein the second source currentgeneration unit comprises: a second sinking section coupled between anoutput terminal of the third bias signal and a ground voltage terminal,wherein the second source current sinks to the ground voltage terminalin response to the first bias signal; a plurality of second sourcingsections coupled between a power supply voltage terminal and a pluralityof second sourcing nodes, respectively, wherein the second sourcecurrent is sourced from the power supply voltage terminal in response tothe third bias signal; and a plurality of second switching sectionscoupled between the plurality of second sourcing nodes, respectively,and the output terminal of the third bias signal, and suitable for beingselectively switched in response to the slope correction signal.
 7. Theramp voltage generator of claim 5, wherein the second ramp voltagegeneration unit comprises: a second mirroring section coupled between apower supply voltage terminal and a plurality of second mirroring nodes,wherein the second source current is sourced from the power supplyvoltage terminal in response to the third bias signal; a third switchingsection coupled between the plurality of second mirroring nodes and anoutput terminal of the fine ramp voltage, and suitable for beingsequentially switched in response to the fine ramp control signal; and asecond resistor section coupled between the output terminal of the fineramp voltage and a ground voltage terminal.
 8. The ramp voltagegenerator of claim 5, further comprising: a storage unit suitable forstoring the slope correction signal.
 9. The ramp voltage generator ofclaim 5, wherein the first source current generation unit comprises: afirst sinking section coupled between an output terminal of the secondbias signal and a ground voltage terminal, wherein the first sourcecurrent sinks to the ground voltage terminal in response to the firstbias signal; and a first sourcing section coupled between a power supplyvoltage terminal and the output terminal of the second bias signal,wherein the first source current is sourced from the power supplyvoltage terminal in response to the second bias signal.
 10. The rampvoltage generator of claim 5, wherein the first ramp voltage generationunit comprises: a first mirroring section coupled between a power supplyvoltage terminal and a plurality of first mirroring nodes, wherein thefirst source current is sourced from the power supply voltage terminalin response to the second bias signal; a first switching section coupledbetween the plurality of first mirroring nodes and an output terminal ofthe coarse ramp voltage, and suitable for being sequentially switched inresponse to the coarse ramp control signal; and a first resistor sectioncoupled between the output terminal of the coarse ramp voltage and aground voltage terminal.
 11. The ramp voltage generator of claim 5,wherein the coarse ramp control signal is generated based on a firstclock, and the fine ramp control signal is generated based on a secondclock with a frequency that is higher than that of the first clock. 12.An image sensing device comprising: a pixel array suitable forgenerating an image signal; an analog-to-digital converter suitable forgenerating a digital signal corresponding to the image signal by using acoarse ramp voltage and a fine ramp voltage; and a ramp voltagegenerator suitable for generating the coarse ramp voltage having a firstslope and the fine ramp voltage having a second slope that is correctedbased on the first slope in response to a bias signal, a coarse rampcontrol signal, and a fine ramp control signal.
 13. The image sensingdevice of claim 12, wherein the second slope is substantially equal tothe first slope.
 14. The image sensing device of claim 12, wherein theramp voltage generator comprises: a correction block suitable forstoring a slope correction signal; a first ramp voltage generation blocksuitable for generating the coarse ramp voltage in response to the biassignal and the coarse ramp control signal; and a second ramp voltagegeneration block suitable for generating the fine ramp voltage inresponse to the bias signal, the fine ramp control signal, and the slopecorrection signal.
 15. The image sensing device of claim 14, wherein thesecond ramp voltage generation block comprises: a second source currentgeneration unit suitable for generating a second source currentcorrected based on the first slope in response to a first bias signaland the slope correction signal, and generating a third bias signalcorresponding to the second source current; and a second ramp voltagegeneration unit suitable for generating a second mirror current that isvaried by a fine unit in response to the third bias signal and the fineramp control signal, and generating the fine ramp voltage based on thesecond mirror current.
 16. The image sensing device of claim 15, whereinthe second source current generation unit comprises: a second sinkingsection coupled between an output terminal of the third bias signal anda ground voltage terminal, wherein the second source current sinks tothe ground voltage terminal in response to the first bias signal; aplurality of second sourcing sections coupled between a power supplyvoltage terminal and a plurality of second sourcing nodes, respectively,wherein the second source current is sourced from the power supplyvoltage terminal in response to the third bias signal; and a pluralityof second switching sections coupled between the plurality of secondsourcing nodes, respectively, and the output terminal of the third biassignal, and suitable for being selectively switched in response to theslope correction signal.
 17. The image sensing device of claim 15,wherein the second ramp voltage generation unit comprises: a secondmirroring section coupled between a power supply voltage terminal and aplurality of second mirroring nodes, wherein the second source currentis sourced from the power supply voltage terminal in response to thethird bias signal; a third switching section coupled between theplurality of second mirroring nodes and an output terminal of the fineramp voltage, and suitable for being sequentially switched in responseto the fine ramp control signal; and a second resistor section coupledbetween the output terminal of the fine ramp voltage and a groundvoltage terminal.
 18. The image sensing device of claim 14, wherein thefirst ramp voltage generation block comprises: a first source currentgeneration unit suitable for generating a first source current inresponse to a first bias signal, and generating a second bias signalcorresponding to the first source current; and a first ramp voltagegeneration unit suitable for generating a first mirror current that isvaried by a coarse unit in response to the second bias signal and thecoarse ramp control signal, and generating the coarse ramp voltage basedon the first mirror current.
 19. The image sensing device of claim 18,wherein the first source current generation unit comprises: a firstsinking section coupled between an output terminal of the second biassignal and a ground voltage terminal, wherein the first source currentsinks to the ground voltage terminal in response to the first biassignal; and a first sourcing section coupled between a power supplyvoltage terminal and the output terminal of the second bias signal,wherein the first source current is sourced from the power supplyvoltage terminal in response to the second bias signal.
 20. The imagesensing device of claim 18, wherein the first ramp voltage generationunit comprises: a first mirroring section coupled between a power supplyvoltage terminal and a plurality of first mirroring nodes, wherein thefirst source current is sourced from the power supply voltage terminalin response to the second bias signal; a first switching section coupledbetween the plurality of first mirroring nodes and an output terminal ofthe coarse ramp voltage, and suitable for being sequentially switched inresponse to the coarse ramp control signal; and a first resistor sectioncoupled between the output terminal of the coarse ramp voltage and aground voltage terminal.